/*
 * Copyright     :  Copyright (C) 2021, Huawei Technologies Co. Ltd.
 * File name     :  pcie5_pcs_typedef.h
 * Project line  :  Platform And Key Technologies Development
 * Department    :  CAD Development Department
 * Version       :  1.0
 * Date          :
 * Description   :  The description of HIPCIECTRL30V200 project
 * Others        :  Generated automatically by nManager V5.1
 * History       :  2021/01/07 09:57:53 Create file
 */

#ifndef PCIE5_PCS_TYPEDEF_H
#define PCIE5_PCS_TYPEDEF_H

/* Define the union csr_rate_change_time_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 5;             /* [4:0] */
        u32 cfg_rate_out_time : 5; /* [9:5] */
        u32 rsv_1 : 22;            /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rate_change_time_u;

/* Define the union csr_power_change_1us_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_1us : 22;       /* [21:0] */
        u32 cfg_txdetrx_loopbk : 1;      /* [22] */
        u32 cfg_txdetrx_loopbk_en : 1;   /* [23] */
        u32 cfg_txelecidle_dly_num : 4;  /* [27:24] */
        u32 cfg_sigdet_rst_rx_msk : 1;   /* [28] */
        u32 cfg_ebuf_rst_rx_en : 1;      /* [29] */
        u32 cfg_blkaln_lpbk_slv_msk : 1; /* [30] */
        u32 cfg_update_fs_en : 1;        /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_power_change_1us_u;

/* Define the union csr_cfg_a_line_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_a_line : 31; /* [30:0] */
        u32 rsv_2 : 1;       /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_a_line_err_u;

/* Define the union csr_cfg_b_line_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_b_line : 31; /* [30:0] */
        u32 rsv_3 : 1;       /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_b_line_err_u;

/* Define the union csr_cfg_c_line_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_c_line : 31; /* [30:0] */
        u32 rsv_4 : 1;       /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_c_line_err_u;

/* Define the union csr_pwr_stay_time_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_min_time : 8;            /* [7:0] */
        u32 cfg_g12_dec_err_relock_num : 12; /* [19:8] */
        u32 cfg_g12_dec_err_relock_en : 1;   /* [20] */
        u32 rsv_5 : 4;                       /* [24:21] */
        u32 rsv_6 : 7;                       /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pwr_stay_time_u;

/* Define the union csr_trace_data_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_trace_data_mask : 22; /* [21:0] */
        u32 rsv_7 : 10;               /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_mask_u;

/* Define the union csr_apb_wr_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 apb_wr_times : 10; /* [9:0] */
        u32 rsv_8 : 22;        /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_apb_wr_num_u;

/* Define the union csr_m_pcs_in18_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_user_bist_data : 20; /* [19:0] */
        u32 cfg_sel_pipe : 1;        /* [20] */
        u32 rsv_9 : 11;              /* [31:21] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_m_pcs_in18_cfg_u;

/* Define the union csr_cfg_trace_port0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_trace_sel_p0 : 2;      /* [1:0] */
        u32 cfg_trace_recap_p0 : 1;    /* [2] */
        u32 cfg_trace_cap_mode_p0 : 1; /* [3] */
        u32 cfg_trace_raddr_p0 : 6;    /* [9:4] */
        u32 rsv_10 : 2;                /* [11:10] */
        u32 trace_last_waddr_p0 : 7;   /* [18:12] */
        u32 rsv_11 : 1;                /* [19] */
        u32 cfg_trace_en : 1;          /* [20] */
        u32 rsv_12 : 11;               /* [31:21] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_trace_port0_u;

/* Define the union csr_m_pcs_eqeval_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_eqeval_en : 1;         /* [0] */
        u32 rsv_13 : 20;               /* [20:1] */
        u32 cfg_p2_phystatus_time : 5; /* [25:21] */
        u32 rsv_14 : 6;                /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_m_pcs_eqeval_cfg_u;

/* Define the union csr_elbuf_empty_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_force_skp_add : 1; /* [0] */
        u32 cfg_force_skp_rem : 1; /* [1] */
        u32 cfg_empty_thres : 4;   /* [5:2] */
        u32 apb_last_waddr : 13;   /* [18:6] */
        u32 rsv_15 : 13;           /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_elbuf_empty_para_u;

/* Define the union csr_recdet_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rec_det_time : 20; /* [19:0] */
        u32 rsv_16 : 12;           /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_recdet_timeout_u;

/* Define the union csr_recdet_interval_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rec_det_interval_time : 14; /* [13:0] */
        u32 rsv_17 : 18;                    /* [31:14] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_recdet_interval_u;

/* Define the union csr_rate_time_out_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_datarate_chge_time : 22; /* [21:0] */
        u32 rsv_18 : 10;                 /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rate_time_out_u;

/* Define the union csr_power_change_time_out_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_1ms : 22; /* [21:0] */
        u32 rsv_19 : 10;           /* [31:22] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_power_change_time_out_u;

/* Define the union csr_eqeval_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_eqeval_time : 20; /* [19:0] */
        u32 rsv_20 : 12;          /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_eqeval_timeout_u;

/* Define the union csr_rx_elecidle_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_21 : 20;           /* [19:0] */
        u32 cfg_rx_sigdet_sel : 1; /* [20] */
        u32 rsv_22 : 11;           /* [31:21] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rx_elecidle_protect_u;

/* Define the union csr_pcie_pcs_eco_rsv0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pcie_pcs_eco_rsv0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcie_pcs_eco_rsv0_u;

/* Define the union csr_pcie_pcs_eco_rsv1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pcie_pcs_eco_rsv1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcie_pcs_eco_rsv1_u;

/* Define the union csr_pcie_pcs_eco_rsv2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pcie_pcs_eco_rsv2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcie_pcs_eco_rsv2_u;

/* Define the union csr_pcie_pcs_eco_rsv3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pcie_pcs_eco_rsv3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcie_pcs_eco_rsv3_u;

/* Define the union csr_pwr_chge_60us_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_60us : 22;   /* [21:0] */
        u32 rsv_23 : 2;               /* [23:22] */
        u32 cfg_g3g4_skp_rem_num : 4; /* [27:24] */
        u32 rsv_24 : 4;               /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pwr_chge_60us_timeout_u;

/* Define the union csr_trace_data_port0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 trace_out_p0 : 31; /* [30:0] */
        u32 rsv_25 : 1;        /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_port0_u;

/* Define the union csr_cfg_trace_port4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_trace_sel_p4 : 2;      /* [1:0] */
        u32 cfg_trace_recap_p4 : 1;    /* [2] */
        u32 cfg_trace_cap_mode_p4 : 1; /* [3] */
        u32 cfg_trace_raddr_p4 : 6;    /* [9:4] */
        u32 rsv_26 : 2;                /* [11:10] */
        u32 trace_last_waddr_p4 : 7;   /* [18:12] */
        u32 rsv_27 : 13;               /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_trace_port4_u;

/* Define the union csr_cfg_trace_port8_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_trace_sel_p8 : 2;      /* [1:0] */
        u32 cfg_trace_recap_p8 : 1;    /* [2] */
        u32 cfg_trace_cap_mode_p8 : 1; /* [3] */
        u32 cfg_trace_raddr_p8 : 6;    /* [9:4] */
        u32 rsv_28 : 2;                /* [11:10] */
        u32 trace_last_waddr_p8 : 7;   /* [18:12] */
        u32 rsv_29 : 13;               /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_trace_port8_u;

/* Define the union csr_cfg_trace_port12_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_trace_sel_p12 : 2;      /* [1:0] */
        u32 cfg_trace_recap_p12 : 1;    /* [2] */
        u32 cfg_trace_cap_mode_p12 : 1; /* [3] */
        u32 cfg_trace_raddr_p12 : 6;    /* [9:4] */
        u32 rsv_30 : 2;                 /* [11:10] */
        u32 trace_last_waddr_p12 : 7;   /* [18:12] */
        u32 rsv_31 : 13;                /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_trace_port12_u;

/* Define the union csr_trace_data_port4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 trace_out_p4 : 31; /* [30:0] */
        u32 rsv_32 : 1;        /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_port4_u;

/* Define the union csr_trace_data_port8_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 trace_out_p8 : 31; /* [30:0] */
        u32 rsv_33 : 1;        /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_port8_u;

/* Define the union csr_trace_data_port12_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 trace_out_p12 : 31; /* [30:0] */
        u32 rsv_34 : 1;         /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_trace_data_port12_u;

/* Define the union csr_trace_ctrl_and_ecc_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_35 : 28;          /* [27:0] */
        u32 cfg_trace_ren_p0 : 1; /* [28] */
        u32 cfg_trace_ren_p4 : 1; /* [29] */
        u32 trace_data_ok_p0 : 1; /* [30] */
        u32 trace_data_ok_p4 : 1; /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_trace_ctrl_and_ecc_0_u;

/* Define the union csr_trace_ctrl_and_ecc_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_36 : 28;           /* [27:0] */
        u32 cfg_trace_ren_p8 : 1;  /* [28] */
        u32 cfg_trace_ren_p12 : 1; /* [29] */
        u32 trace_data_ok_p8 : 1;  /* [30] */
        u32 trace_data_ok_p12 : 1; /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_trace_ctrl_and_ecc_1_u;

/* Define the union csr_pcs_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_ind : 16; /* [15:0] */
        u32 rsv_37 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_status_u;

/* Define the union csr_pcs_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_set : 16; /* [15:0] */
        u32 rsv_38 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_set_u;

/* Define the union csr_pcs_intr_msk_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_mask : 16; /* [15:0] */
        u32 rsv_39 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_msk_u;

/* Define the union csr_pcs_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_ro : 16; /* [15:0] */
        u32 rsv_40 : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ro_u;

/* Define the union csr_rx_eleceidle_prt_num_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxelecidle_protect_num : 20; /* [19:0] */
        u32 rsv_41 : 12;                     /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rx_eleceidle_prt_num_u;

/* Define the union csr_rx_rcv_eios_width_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_rcv_eios_width : 12; /* [11:0] */
        u32 rsv_42 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rx_rcv_eios_width_u;

/* Define the union csr_rxvalid_protecntion_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_43 : 2;               /* [1:0] */
        u32 cfg_rxvalid_prt_num : 24; /* [25:2] */
        u32 rsv_44 : 6;               /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rxvalid_protecntion_para_u;

/* Define the union csr_inject_1bit_error_num_s_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 inject_1bit_err_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_inject_1bit_error_num_s_u;

/* Define the union csr_inject_2bit_error_num_s_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 inject_2bit_err_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_inject_2bit_error_num_s_u;

/* Define the union csr_inject_1cycle_error_num_s_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 inject_1cycle_err_num : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_inject_1cycle_error_num_s_u;

/* Define the union csr_rx_margin_en_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxmargin_en_time : 29; /* [28:0] */
        u32 rsv_45 : 3;                /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rx_margin_en_para_u;

/* Define the union csr_rx_margin_rdy_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxmargin_rdy_time : 26; /* [25:0] */
        u32 rsv_46 : 6;                 /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rx_margin_rdy_para_u;

/* Define the union csr_fs_calc_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_47 : 1;              /* [0] */
        u32 cfg_tx_fs_en : 1;        /* [1] */
        u32 cfg_tx_fs : 6;           /* [7:2] */
        u32 cfg_tx_fs_final_sel : 3; /* [10:8] */
        u32 rsv_48 : 1;              /* [11] */
        u32 adpt_status_clr_en : 1;  /* [12] */
        u32 rsv_49 : 19;             /* [31:13] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_fs_calc_u;

/* Define the union csr_fs_calc_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_tx_fs_timeout : 30; /* [29:0] */
        u32 rsv_50 : 2;             /* [31:30] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_fs_calc_timeout_u;

/* Define the union csr_fs_calc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_xport_status : 28; /* [27:0] */
        u32 rsv_51 : 4;            /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_fs_calc_status_u;

/* Define the union csr_pcs_status_ren_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_wake_status_ren : 1;      /* [0] */
        u32 cfg_main_status_ren : 1;      /* [1] */
        u32 cfg_eqeval_status_ren : 1;    /* [2] */
        u32 cfg_pwr_chge_status_ren : 1;  /* [3] */
        u32 cfg_recv_det_status_ren : 1;  /* [4] */
        u32 cfg_rxmargin_status_ren : 1;  /* [5] */
        u32 cfg_g12_dec_err_cnt_ren : 1;  /* [6] */
        u32 cfg_g12_align_status_ren : 1; /* [7] */
        u32 cfg_g34_align_status_ren : 1; /* [8] */
        u32 cfg_ebuf_status_ren : 1;      /* [9] */
        u32 cfg_bist_status_ren : 1;      /* [10] */
        u32 cfg_g34_enc_status_ren : 1;   /* [11] */
        u32 rsv_52 : 20;                  /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_status_ren_u;

/* Define the union csr_rxtx_status_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxtx_status_timeout : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_rxtx_status_timeout_u;

/* Define the union csr_pcs_version_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_version : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_version_u;

/* Define the union csr_pcs_release_date_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_release_date : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_release_date_u;

/* Define the union csr_pcs_port_link_mode_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_port0_mode : 3;  /* [2:0] */
        u32 rsv_53 : 1;          /* [3] */
        u32 cfg_port2_mode : 3;  /* [6:4] */
        u32 rsv_54 : 1;          /* [7] */
        u32 cfg_port4_mode : 3;  /* [10:8] */
        u32 rsv_55 : 1;          /* [11] */
        u32 cfg_port6_mode : 3;  /* [14:12] */
        u32 rsv_56 : 1;          /* [15] */
        u32 cfg_port8_mode : 3;  /* [18:16] */
        u32 rsv_57 : 1;          /* [19] */
        u32 cfg_port10_mode : 3; /* [22:20] */
        u32 rsv_58 : 1;          /* [23] */
        u32 cfg_port12_mode : 3; /* [26:24] */
        u32 rsv_59 : 1;          /* [27] */
        u32 cfg_port14_mode : 3; /* [30:28] */
        u32 rsv_60 : 1;          /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_port_link_mode_u;

/* Define the union csr_cfg_a_line_l_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_a_line_l : 23; /* [22:0] */
        u32 rsv_61 : 9;        /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_a_line_l_err_u;

/* Define the union csr_cfg_b_line_l_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_b_line_l : 23; /* [22:0] */
        u32 rsv_62 : 9;        /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_b_line_l_err_u;

/* Define the union csr_cfg_c_line_l_err_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_c_line_l : 23; /* [22:0] */
        u32 rsv_63 : 9;        /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_cfg_c_line_l_err_u;

/* Define the union csr_fs_calc_rdy_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 sds2pcs_tx_fs_rdy : 16; /* [15:0] */
        u32 rsv_64 : 16;            /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_fs_calc_rdy_u;

/* Define the union csr_pma_rxeq_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_txdeemph_mux : 18;         /* [17:0] */
        u32 rsv_65 : 2;                    /* [19:18] */
        u32 cfg_pma_txdeemph_lane_sel : 4; /* [23:20] */
        u32 cfg_pma_txdeemph_rd_en : 1;    /* [24] */
        u32 rsv_66 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_rxeq_dfx_u;

/* Define the union csr_serdes_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 serdes_dfx_status : 24; /* [23:0] */
        u32 rsv_67 : 8;             /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_serdes_dfx_u;

/* Define the union csr_int_type_sel_ce_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ce_int_sel : 16; /* [15:0] */
        u32 rsv_68 : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_int_type_sel_ce_u;

/* Define the union csr_int_type_sel_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 nfe_int_sel : 16; /* [15:0] */
        u32 rsv_69 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_int_type_sel_nfe_u;

/* Define the union csr_int_type_sel_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 fe_int_sel : 16; /* [15:0] */
        u32 rsv_70 : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_int_type_sel_fe_u;

/* Define the union csr_int_type_sel_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ni_int_sel : 16; /* [15:0] */
        u32 rsv_71 : 16;     /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_int_type_sel_ni_u;

/* Define the union csr_pcs_intr_nfe_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_nfe_ind : 16; /* [15:0] */
        u32 rsv_72 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_nfe_status_u;

/* Define the union csr_pcs_intr_nfe_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_nfe_set : 16; /* [15:0] */
        u32 rsv_73 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_nfe_set_u;

/* Define the union csr_pcs_intr_nfe_msk_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_nfe_mask : 16; /* [15:0] */
        u32 rsv_74 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_nfe_msk_u;

/* Define the union csr_pcs_intr_nfe_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_nfe_ro : 16; /* [15:0] */
        u32 rsv_75 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_nfe_ro_u;

/* Define the union csr_pcs_intr_fe_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_fe_ind : 16; /* [15:0] */
        u32 rsv_76 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_fe_status_u;

/* Define the union csr_pcs_intr_fe_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_fe_set : 16; /* [15:0] */
        u32 rsv_77 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_fe_set_u;

/* Define the union csr_pcs_intr_fe_msk_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_fe_mask : 16; /* [15:0] */
        u32 rsv_78 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_fe_msk_u;

/* Define the union csr_pcs_intr_fe_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_fe_ro : 16; /* [15:0] */
        u32 rsv_79 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_fe_ro_u;

/* Define the union csr_pcs_intr_ni_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_ni_ind : 16; /* [15:0] */
        u32 rsv_80 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ni_status_u;

/* Define the union csr_pcs_intr_ni_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_ni_set : 16; /* [15:0] */
        u32 rsv_81 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ni_set_u;

/* Define the union csr_pcs_intr_ni_msk_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_ni_mask : 16; /* [15:0] */
        u32 rsv_82 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ni_msk_u;

/* Define the union csr_pcs_intr_ni_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_int_ni_ro : 16; /* [15:0] */
        u32 rsv_83 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_intr_ni_ro_u;

/* Define the union csr_power_chge_prt_mode_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_protect_mode_p0s : 4;   /* [3:0] */
        u32 cfg_protect_mode_p1 : 4;    /* [7:4] */
        u32 cfg_protect_mode_p2 : 4;    /* [11:8] */
        u32 cfg_protect_mode_rxl0s : 4; /* [15:12] */
        u32 rsv_84 : 16;                /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_power_chge_prt_mode_u;

/* Define the union csr_power_chge_wait_idle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_p0s_wait_p1p2_idle_dis : 1; /* [0] */
        u32 cfg_p1_wait_p2_idle_dis : 1;    /* [1] */
        u32 cfg_mclk0_always_on : 1;        /* [2] */
        u32 cfg_pll0_never_calib : 1;       /* [3] */
        u32 cfg_ccix_25g_20bit_mode : 1;    /* [4] */
        u32 cfg_rxtx_status_dly : 11;       /* [15:5] */
        u32 cfg_pcs_cdc_txbuf_mode : 16;    /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_power_chge_wait_idle_u;

/* Define the union csr_pcs_cdc_dptx_fifo_thres_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_dptx_syncbuf_ae_th : 6; /* [5:0] */
        u32 rsv_85 : 2;                     /* [7:6] */
        u32 cfg_cdc_dptx_syncbuf_af_th : 6; /* [13:8] */
        u32 rsv_86 : 2;                     /* [15:14] */
        u32 cfg_cdc_dptx_asynbuf_ae_th : 6; /* [21:16] */
        u32 rsv_87 : 2;                     /* [23:22] */
        u32 cfg_cdc_dptx_asynbuf_af_th : 6; /* [29:24] */
        u32 cfg_glbcfg_from_bus : 1;        /* [30] */
        u32 rsv_88 : 1;                     /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_dptx_fifo_thres_u;

/* Define the union csr_pcs_lane2macro_map_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lane2macro_mapping_m0 : 16; /* [15:0] */
        u32 cfg_lane2macro_mapping_m1 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_lane2macro_map_0_u;

/* Define the union csr_pcs_lane2macro_map_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lane2macro_mapping_m2 : 16; /* [15:0] */
        u32 cfg_lane2macro_mapping_m3 : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_lane2macro_map_1_u;

/* Define the union csr_pcs_cdc_global_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_global_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_status0_u;

/* Define the union csr_pcs_cdc_global_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_global_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_status1_u;

/* Define the union csr_pcs_cdc_global_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_global_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_status2_u;

/* Define the union csr_pcs_cdc_global_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_global_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_status3_u;

/* Define the union csr_pcs_cdc_global_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_global_cfg : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_global_cfg_u;

/* Define the union csr_pcs_cdc_skp_th_g1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_skpadd_th_g1 : 13; /* [12:0] */
        u32 rsv_89 : 3;                /* [15:13] */
        u32 cfg_cdc_skprem_th_g1 : 13; /* [28:16] */
        u32 rsv_90 : 3;                /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g1_u;

/* Define the union csr_pcs_cdc_skp_th_g2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_skpadd_th_g2 : 13; /* [12:0] */
        u32 rsv_91 : 3;                /* [15:13] */
        u32 cfg_cdc_skprem_th_g2 : 13; /* [28:16] */
        u32 rsv_92 : 3;                /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g2_u;

/* Define the union csr_pcs_cdc_skp_th_g3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_skpadd_th_g3 : 13; /* [12:0] */
        u32 rsv_93 : 3;                /* [15:13] */
        u32 cfg_cdc_skprem_th_g3 : 13; /* [28:16] */
        u32 rsv_94 : 3;                /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g3_u;

/* Define the union csr_pcs_cdc_skp_th_g4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_skpadd_th_g4 : 13; /* [12:0] */
        u32 rsv_95 : 3;                /* [15:13] */
        u32 cfg_cdc_skprem_th_g4 : 13; /* [28:16] */
        u32 rsv_96 : 3;                /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g4_u;

/* Define the union csr_pcs_cdc_skp_th_g5_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_skpadd_th_g5 : 13; /* [12:0] */
        u32 rsv_97 : 3;                /* [15:13] */
        u32 cfg_cdc_skprem_th_g5 : 13; /* [28:16] */
        u32 rsv_98 : 3;                /* [31:29] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_th_g5_u;

/* Define the union csr_pcs_cdc_skp_proc_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_skp_add_en : 1; /* [0] */
        u32 cfg_cdc_skp_rem_en : 1; /* [1] */
        u32 rsv_99 : 30;            /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_proc_en_u;

/* Define the union csr_pcs_cdc_skp_req_dly_th_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_skp_req_dly_th : 7; /* [6:0] */
        u32 rsv_100 : 25;               /* [31:7] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_skp_req_dly_th_u;

/* Define the union csr_pcs_cdc_tx_ele_exit_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_cdc_tx_exit_ele_protect_value : 3; /* [2:0] */
        u32 cfg_cdc_tx_exit_ele_protect_en : 1;    /* [3] */
        u32 rsv_101 : 28;                          /* [31:4] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_cdc_tx_ele_exit_protect_u;

/* Define the union csr_retimer_function_switch_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_retimer_fw_symbol_unlock_en : 1;   /* [0] */
        u32 cfg_retimer_fw_dec_err_replace_en : 1; /* [1] */
        u32 cfg_retimer_udfl_data_replace_en : 1;  /* [2] */
        u32 rsv_102 : 29;                          /* [31:3] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_retimer_function_switch_u;

/* Define the union csr_pwrchge_physts_dly_param_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwrchge_physts_dly_param : 26; /* [25:0] */
        u32 cfg_ratechge_in_px : 5;            /* [30:26] */
        u32 rsv_103 : 1;                       /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pwrchge_physts_dly_param_u;

/* Define the union csr_pma_cmd_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwrchge_lane_timeout_p0s : 12; /* [11:0] */
        u32 cfg_rx_sync_head : 2;              /* [13:12] */
        u32 rsv_104 : 18;                      /* [31:14] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_para_0_u;

/* Define the union csr_pma_cmd_para_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwrchge_lane_timeout_p1 : 12; /* [11:0] */
        u32 rsv_105 : 20;                     /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_para_1_u;

/* Define the union csr_pma_cmd_para_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwrchge_lane_timeout_p2 : 12; /* [11:0] */
        u32 rsv_106 : 20;                     /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_para_2_u;

/* Define the union csr_pma_cmd_sts_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_p0s : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_0_u;

/* Define the union csr_pma_cmd_sts_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_p1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_1_u;

/* Define the union csr_pma_cmd_sts_2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_p2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_2_u;

/* Define the union csr_pma_cmd_sts_3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_txbeacon : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_3_u;

/* Define the union csr_pma_cmd_sts_4_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_rxl0s : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_4_u;

/* Define the union csr_pma_cmd_sts_0_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_p0s_0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_0_1_u;

/* Define the union csr_pma_cmd_sts_1_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_p1_0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_1_1_u;

/* Define the union csr_pma_cmd_sts_2_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_p2_0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_2_1_u;

/* Define the union csr_pma_cmd_sts_3_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_txbeacon_0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_3_1_u;

/* Define the union csr_pma_cmd_sts_4_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pma_cmd_sts_rxl0s_0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pma_cmd_sts_4_1_u;

/* Define the union csr_pcs_clk_icg_en_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_pcs_logic : 16;     /* [15:0] */
        u32 icg_en_pcs_logic_div : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_clk_icg_en_0_u;

/* Define the union csr_pcs_clk_icg_en_1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 icg_en_pcs_tx : 16; /* [15:0] */
        u32 icg_en_pcs_rx : 16; /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_clk_icg_en_1_u;

/* Define the union csr_pcs_timer_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_100ns_timer : 8; /* [7:0] */
        u32 cfg_1us_timer : 12;  /* [19:8] */
        u32 rsv_107 : 12;        /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_timer_cfg_u;

/* Define the union csr_pcs_eios_clr_lock_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_eios_clr_lock_en : 1; /* [0] */
        u32 cfg_2skp_rem_dis : 1;     /* [1] */
        u32 rsv_108 : 30;             /* [31:2] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_eios_clr_lock_u;

/* Define the union csr_pcs_serial_intve_time_p0s_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lane_interval_time_p0s : 24; /* [23:0] */
        u32 rsv_109 : 8;                     /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_p0s_u;

/* Define the union csr_pcs_serial_intve_time_p1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lane_interval_time_p1 : 24; /* [23:0] */
        u32 rsv_110 : 8;                    /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_p1_u;

/* Define the union csr_pcs_serial_intve_time_p2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lane_interval_time_p2 : 24; /* [23:0] */
        u32 rsv_111 : 8;                    /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_p2_u;

/* Define the union csr_pcs_serial_intve_time_rxl0s_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lane_interval_time_rxl0s : 24; /* [23:0] */
        u32 rsv_112 : 8;                       /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_rxl0s_u;

/* Define the union csr_pcs_serial_intve_time_mode_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_lane_timer_mode_p0s : 1;    /* [0] */
        u32 rsv_113 : 3;                    /* [3:1] */
        u32 cfg_lane_timer_mode_p1 : 1;     /* [4] */
        u32 rsv_114 : 3;                    /* [7:5] */
        u32 cfg_lane_timer_mode_p2 : 1;     /* [8] */
        u32 rsv_115 : 3;                    /* [11:9] */
        u32 cfg_lane_timer_mode_rxl0s : 1;  /* [12] */
        u32 rsv_116 : 3;                    /* [15:13] */
        u32 cfg_refclk_serial_en : 1;       /* [16] */
        u32 cfg_refclk_timer_mode : 1;      /* [17] */
        u32 cfg_refclk_timeout_cnt_clr : 1; /* [18] */
        u32 rsv_117 : 13;                   /* [31:19] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_mode_u;

/* Define the union csr_pcs_serial_intve_time_refclk_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_refclk_interval_time : 24; /* [23:0] */
        u32 rsv_118 : 8;                   /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_serial_intve_time_refclk_u;

/* Define the union csr_pcs_refclk_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 refclk_ctrl_status : 20; /* [19:0] */
        u32 rsv_119 : 12;            /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_glb_reg_pcs_refclk_status_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_0_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_1_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_2_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_3_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_4_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_5_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_6_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_7_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_8_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_9_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_10_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_11_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_12_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_13_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_14_pcs_pwrchge_cnt_u;

/* Define the union csr_m_pcs_in13_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_0 : 3;                 /* [2:0] */
        u32 cfg_rx_sigdet : 1;         /* [3] */
        u32 cfg_pll_lock : 1;          /* [4] */
        u32 cfg_bist_en : 1;           /* [5] */
        u32 cfg_bist_rst_n : 1;        /* [6] */
        u32 cfg_bist_insert_error : 1; /* [7] */
        u32 cfg_bist_mode : 4;         /* [11:8] */
        u32 cfg_osi_en : 1;            /* [12] */
        u32 rsv_1 : 1;                 /* [13] */
        u32 rsv_2 : 1;                 /* [14] */
        u32 cfg_rx_sigdet_en : 1;      /* [15] */
        u32 cfg_txswing : 1;           /* [16] */
        u32 cfg_pll_lock_en : 1;       /* [17] */
        u32 cfg_txmargin : 3;          /* [20:18] */
        u32 cfg_data_rate_en : 1;      /* [21] */
        u32 rsv_3 : 2;                 /* [23:22] */
        u32 cfg_loopback_mode : 3;     /* [26:24] */
        u32 rsv_4 : 1;                 /* [27] */
        u32 cfg_data_rate : 4;         /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_m_pcs_in13_cfg_u;

/* Define the union csr_m_pcs_in14_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_loc_lf : 6;        /* [5:0] */
        u32 cfg_loc_fs : 6;        /* [11:6] */
        u32 cfg_loc_lf_fs_en : 1;  /* [12] */
        u32 cfg_dir_feedbk : 6;    /* [18:13] */
        u32 cfg_fom_feedbk : 8;    /* [26:19] */
        u32 cfg_eye_feedbk_en : 1; /* [27] */
        u32 rsv_5 : 4;             /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_m_pcs_in14_cfg_u;

/* Define the union csr_m_pcs_in15_cfg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_6 : 7;                 /* [6:0] */
        u32 cfg_tx_deemph : 18;        /* [24:7] */
        u32 cfg_pcs_sim_en : 1;        /* [25] */
        u32 cfg_rx_sigdet_reverse : 1; /* [26] */
        u32 cfg_no_sds : 1;            /* [27] */
        u32 cfg_rate : 2;              /* [29:28] */
        u32 cfg_rate_en : 1;           /* [30] */
        u32 rsv_7 : 1;                 /* [31] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_m_pcs_in15_cfg_u;

/* Define the union csr_mux_los_alos_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_los_alos_sel : 1;         /* [0] */
        u32 cfg_rxtx_status_en : 1;       /* [1] */
        u32 cfg_rxtx_status : 1;          /* [2] */
        u32 cfg_eyediag_done_en : 1;      /* [3] */
        u32 cfg_eyediag_done : 1;         /* [4] */
        u32 cfg_detectrx_rdy_en : 1;      /* [5] */
        u32 cfg_detectrx_rdy : 1;         /* [6] */
        u32 cfg_far_end_serial_lp : 1;    /* [7] */
        u32 rsv_8 : 1;                    /* [8] */
        u32 cfg_bist_dwidth : 2;          /* [10:9] */
        u32 cfg_blockalign_en : 1;        /* [11] */
        u32 cfg_blockalign : 1;           /* [12] */
        u32 cfg_g3_head_chk_en : 2;       /* [14:13] */
        u32 cfg_blockalign_state_sel : 1; /* [15] */
        u32 cfg_eios_mask_dec_err : 2;    /* [17:16] */
        u32 cfg_rxmargin_en : 1;          /* [18] */
        u32 cfg_rxmargin_sel : 1;         /* [19] */
        u32 cfg_gen3_8bit_mode : 1;       /* [20] */
        u32 cfg_low_latency_ebuf : 1;     /* [21] */
        u32 cfg_eieos_sel : 1;            /* [22] */
        u32 rsv_9 : 9;                    /* [31:23] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_mux_los_alos_u;

/* Define the union csr_sds_cfg_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rx_preset_hint : 3;    /* [2:0] */
        u32 cfg_rx_preset_hint_en : 1; /* [3] */
        u32 cfg_detectrx_out_en : 1;   /* [4] */
        u32 cfg_detectrx_out : 1;      /* [5] */
        u32 cfg_powerstate_en : 1;     /* [6] */
        u32 rsv_10 : 3;                /* [9:7] */
        u32 cfg_txeleidle_en : 1;      /* [10] */
        u32 cfg_txeleidle : 1;         /* [11] */
        u32 rsv_11 : 2;                /* [13:12] */
        u32 cfg_rxvalid_en : 1;        /* [14] */
        u32 cfg_rxvalid : 1;           /* [15] */
        u32 rsv_12 : 2;                /* [17:16] */
        u32 cfg_powerdown_en : 1;      /* [18] */
        u32 rsv_13 : 1;                /* [19] */
        u32 cfg_powerdown : 4;         /* [23:20] */
        u32 cfg_powerstate : 4;        /* [27:24] */
        u32 rsv_14 : 4;                /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_sds_cfg_reg_u;

/* Define the union csr_m_pcs_rpt_reg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_bist_sync_done : 1; /* [0] */
        u32 ch_bist_err_cnt : 10;  /* [10:1] */
        u32 rsv_15 : 1;            /* [11] */
        u32 ch_bist_check_err : 1; /* [12] */
        u32 rsv_16 : 1;            /* [13] */
        u32 ch_rxeqeval : 1;       /* [14] */
        u32 rxstatus : 3;          /* [17:15] */
        u32 g3_align_state : 3;    /* [20:18] */
        u32 g12_align_state : 3;   /* [23:21] */
        u32 rsv_17 : 8;            /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_m_pcs_rpt_reg_u;

/* Define the union csr_serdes_status_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ch_rx_sigdet : 1;      /* [0] */
        u32 ch_rx_asigdet : 1;     /* [1] */
        u32 ch_rxtx_status : 1;    /* [2] */
        u32 ch_eyediag_done : 1;   /* [3] */
        u32 ch_detectrx_ready : 1; /* [4] */
        u32 rsv_18 : 27;           /* [31:5] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_serdes_status_rpt_u;

/* Define the union csr_time_out_rpt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rsv_19 : 4;     /* [3:0] */
        u32 ch_skp_add : 1; /* [4] */
        u32 ch_skp_rem : 1; /* [5] */
        u32 rsv_20 : 26;    /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_time_out_rpt_u;

/* Define the union csr_polarity_rxvalid_rxelecidle_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeleidle_prot_en : 1; /* [0] */
        u32 cfg_rxvalid_out_en : 1;    /* [1] */
        u32 cfg_rxpolarity : 1;        /* [2] */
        u32 cfg_rxpolarity_en : 1;     /* [3] */
        u32 cfg_inject_err : 1;        /* [4] */
        u32 cfg_inject_err_tx : 1;     /* [5] */
        u32 rsv_21 : 26;               /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_polarity_rxvalid_rxelecidle_u;

/* Define the union csr_status_clr_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_pwr_chge_timeout_clr : 1;  /* [0] */
        u32 cfg_rec_det_timeout_clr : 1;   /* [1] */
        u32 cfg_pll_loss_lock_clr : 1;     /* [2] */
        u32 cfg_rate_chge_timeout_clr : 1; /* [3] */
        u32 cfg_eqeval_timeout_clr : 1;    /* [4] */
        u32 cfg_gen3_blk_err_clr : 1;      /* [5] */
        u32 cfg_gen3_h_err_clr : 1;        /* [6] */
        u32 cfg_ebuf_ovrflow_err_clr : 1;  /* [7] */
        u32 cfg_ebuf_undflow_err_clr : 1;  /* [8] */
        u32 cfg_g3_dec_h_err_clr : 1;      /* [9] */
        u32 cfg_g12_loss_alg_cnt_clr : 1;  /* [10] */
        u32 cfg_gen12_dec_err_cnt_clr : 1; /* [11] */
        u32 rsv_22 : 20;                   /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_status_clr_u;

/* Define the union csr_ebuf_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 ebuf_status : 20; /* [19:0] */
        u32 rsv_23 : 12;      /* [31:20] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_ebuf_status_u;

/* Define the union csr_gen3_dec_enc_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 gen3_enc_status : 16; /* [15:0] */
        u32 g3_dec_h_err_num : 8; /* [23:16] */
        u32 main_status : 8;      /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_gen3_dec_enc_status_u;

/* Define the union csr_wake_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 wake_status : 24;       /* [23:0] */
        u32 gen12_loss_aln_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_wake_status_u;

/* Define the union csr_recv_det_or_pwr_chage_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 recv_det_status : 12;     /* [11:0] */
        u32 pwr_chge_status : 12;     /* [23:12] */
        u32 gen12_decode_err_cnt : 8; /* [31:24] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_recv_det_or_pwr_chage_u;

/* Define the union csr_eqeval_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 eqeval_status : 18; /* [17:0] */
        u32 rsv_24 : 14;        /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_eqeval_status_u;

/* Define the union csr_rate_chge_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rate_chge_status : 16; /* [15:0] */
        u32 rsv_25 : 16;           /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_rate_chge_status0_u;

/* Define the union csr_lane_intr_ro_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro : 16; /* [15:0] */
        u32 rsv_26 : 16;      /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_ro_u;

/* Define the union csr_lane_intr_set_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_set : 16; /* [15:0] */
        u32 rsv_27 : 16;       /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_set_u;

/* Define the union csr_lane_intr_mask_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_mask : 16; /* [15:0] */
        u32 rsv_28 : 16;        /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_mask_u;

/* Define the union csr_lane_intr_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_status : 16; /* [15:0] */
        u32 rsv_29 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_status_u;

/* Define the union csr_lane_ebuf_para_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g12_rd_thres : 5;          /* [4:0] */
        u32 cfg_g34_rd_thres : 5;          /* [9:5] */
        u32 cfg_afull_off_thres : 5;       /* [14:10] */
        u32 cfg_afull_on_thres : 5;        /* [19:15] */
        u32 cfg_mac_rximpedance_ft_en : 1; /* [20] */
        u32 cfg_sds_rximpedance_en : 1;    /* [21] */
        u32 cfg_sds_rximpedance : 1;       /* [22] */
        u32 cfg_fiber_en : 1;              /* [23] */
        u32 cfg_pma_rxdetect_dis : 1;      /* [24] */
        u32 rsv_30 : 7;                    /* [31:25] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_ebuf_para_u;

/* Define the union csr_rx_margin_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxmargin_status : 15; /* [14:0] */
        u32 rsv_31 : 17;          /* [31:15] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_rx_margin_status_u;

/* Define the union csr_rx_margin_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxm_rdy_timeout_pulse : 12; /* [11:0] */
        u32 rsv_32 : 20;                /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_rx_margin_timeout_u;

/* Define the union csr_rxeq_coarsetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_coarsetune_timeout : 8; /* [7:0] */
        u32 rsv_33 : 24;                 /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_rxeq_coarsetune_timeout_u;

/* Define the union csr_rxeq_finetune_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxeq_finetune_timeout : 8; /* [7:0] */
        u32 rsv_34 : 24;               /* [31:8] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_rxeq_finetune_timeout_u;

/* Define the union csr_detect_clk_flg_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 dfx_tclk_detect_req : 1; /* [0] */
        u32 dfx_tclk_exist : 1;      /* [1] */
        u32 rsv_35 : 2;              /* [3:2] */
        u32 dfx_rclk_detect_req : 1; /* [4] */
        u32 dfx_rclk_exist : 1;      /* [5] */
        u32 rsv_36 : 26;             /* [31:6] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_detect_clk_flg_u;

/* Define the union csr_msg_bus_dfx_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status : 10; /* [9:0] */
        u32 rsv_37 : 2;          /* [11:10] */
        u32 eq_adpt_status : 20; /* [31:12] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_msg_bus_dfx_u;

/* Define the union csr_rxeq_start_ctrl_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_rxeq_ft_start : 1;       /* [0] */
        u32 cfg_rxeq_ft_start_en : 1;    /* [1] */
        u32 cfg_rxeq_ct_start : 1;       /* [2] */
        u32 cfg_rxeq_ct_start_en : 1;    /* [3] */
        u32 cfg_lane_off_pma_px : 4;     /* [7:4] */
        u32 cfg_lane_off_pma_px_en : 1;  /* [8] */
        u32 rsv_38 : 3;                  /* [11:9] */
        u32 cfg_lane_off_pipe_px : 4;    /* [15:12] */
        u32 cfg_lane_off_pipe_px_en : 1; /* [16] */
        u32 rsv_39 : 15;                 /* [31:17] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_rxeq_start_ctrl_u;

/* Define the union csr_lane_intr_ro_nfe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_nfe : 16; /* [15:0] */
        u32 rsv_40 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_ro_nfe_u;

/* Define the union csr_lane_intr_ro_fe_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_fe : 16; /* [15:0] */
        u32 rsv_41 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_ro_fe_u;

/* Define the union csr_lane_intr_ro_ni_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 lane_int_ro_ni : 16; /* [15:0] */
        u32 rsv_42 : 16;         /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_lane_intr_ro_ni_u;

/* Define the union csr_phy2mac_msg_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 msg_bus_status_p2m : 16;        /* [15:0] */
        u32 msg_bus_status_m2p : 4;         /* [19:16] */
        u32 msg_bus_m2p_fifo_overflow : 2;  /* [21:20] */
        u32 msg_bus_m2p_fifo_underflow : 2; /* [23:22] */
        u32 msg_bus_p2m_fifo_overflow : 2;  /* [25:24] */
        u32 msg_bus_p2m_fifo_underflow : 2; /* [27:26] */
        u32 rsv_43 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_phy2mac_msg_status_u;

/* Define the union csr_pcs_msg_pin_en_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_pin_sel : 16; /* [15:0] */
        u32 rsv_44 : 16;          /* [31:16] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_msg_pin_en_u;

/* Define the union csr_pcs_msg_time_protect_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_msg_prot_para : 20;       /* [19:0] */
        u32 rsv_45 : 4;                   /* [23:20] */
        u32 cfg_phy_addr0_to_sds_dis : 1; /* [24] */
        u32 cfg_phy_addr1_to_sds_dis : 1; /* [25] */
        u32 rsv_46 : 6;                   /* [31:26] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_msg_time_protect_u;

/* Define the union csr_txbeacon_rxl0s_timeout_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_txbeacon_timeout_para : 12; /* [11:0] */
        u32 rsv_47 : 4;                     /* [15:12] */
        u32 cfg_rxl0s_timeout_para : 12;    /* [27:16] */
        u32 rsv_48 : 4;                     /* [31:28] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_txbeacon_rxl0s_timeout_u;

/* Define the union csr_pcs_misc_ctrl_para_0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 cfg_g5_eieos_mux : 1;                /* [0] */
        u32 cfg_g25_eieos_mux : 1;               /* [1] */
        u32 cfg_g20_eieos_mux : 1;               /* [2] */
        u32 cfg_g5_align_2eieos_en : 1;          /* [3] */
        u32 cfg_rcv_eios_mask : 1;               /* [4] */
        u32 cfg_elbuf_mode_vendor : 1;           /* [5] */
        u32 cfg_elbuf_depth_vendor : 1;          /* [6] */
        u32 cfg_lpbk_slv_delay_en : 1;           /* [7] */
        u32 cfg_tx_polarity_revert : 1;          /* [8] */
        u32 cfg_rx_beacon_det_msk : 1;           /* [9] */
        u32 rsv_49 : 1;                          /* [10] */
        u32 cfg_g3_high_txidle_delay_en : 1;     /* [11] */
        u32 cfg_alos_debounce_force_idle_en : 1; /* [12] */
        u32 cfg_fix_rxdatavld_high_msk : 1;      /* [13] */
        u32 cfg_lpbk_slv_elbuf_rd_ctrl : 1;      /* [14] */
        u32 cfg_lpbk_slv_flush_dis : 1;          /* [15] */
        u32 cfg_lane0_location : 1;              /* [16] */
        u32 cfg_lane0_location_en : 1;           /* [17] */
        u32 rsv_50 : 14;                         /* [31:18] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_misc_ctrl_para_0_u;

/* Define the union csr_pcs_beacon_rxl0s_status_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 tx_beacon_status : 4;  /* [3:0] */
        u32 rxl0s_status : 4;      /* [7:4] */
        u32 tx_beacon_timeout : 2; /* [9:8] */
        u32 rsv_51 : 22;           /* [31:10] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_beacon_rxl0s_status_u;

/* Define the union csr_pcs_cdc_lane_status0_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status0 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_cdc_lane_status0_u;

/* Define the union csr_pcs_cdc_lane_status1_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status1 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_cdc_lane_status1_u;

/* Define the union csr_pcs_cdc_lane_status2_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status2 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_cdc_lane_status2_u;

/* Define the union csr_pcs_cdc_lane_status3_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pcs_cdc_lane_status3 : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_cdc_lane_status3_u;

/* Define the union csr_pcs_rxtx_status_in_low_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 rxtx_status_stay_low_time : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_rxtx_status_in_low_u;

/* Define the union csr_pcs_pwrchge_cnt_u */
typedef union {
    /* Define the struct bits */
    struct {
        u32 pwrchge_cnt : 32; /* [31:0] */
    } bits;

    /* Define an unsigned member */
    u32 value;
} csr_pcie5_hipciec50_pcs_lane_reg_15_pcs_pwrchge_cnt_u;

#endif
